1. Field of the Invention
The present invention relates generally to a programmable clock generator for integrated circuits, very large scale integrated circuits (VLSI), and ultra large scale integrated circuits (ULSI). More particularly, the present invention relates to a programmable clock generator for selecting optimal non-overlapping clocking signals for controlling elements on a chip.
2. Related Art
Most microprocessor chips operate as control driven, synchronous sequential systems. This means the sequence of operations in the system is synchronized by a master clock signal (usually an external clock). This clock signal is usually one of the forms shown in FIG. 1; which illustrates a square wave with a 50% duty cycle.
The master clock signal allows system operations to occur at regularly spaced-intervals. In particular, operations on the chip are made to take place at times when the clock signal is making a transition from low-to-high or from high-to-low; rising edge 102 or falling edge 104, respectively.
Many microprocessor chips have their timing controlled by two or more related clock signals generated by an on-chip clock generator based on the master clock signal. FIG. 2A illustrates one such combination utilizing two clock signals identified by .phi.1 and .phi.2. This clocking arrangement provides four different edges and three different states per period, compared to only two edges and two states per period provided with a single clock signal as shown in FIG. 1. FIG. 2B illustrates examples of the three possible states for clock signals .phi.1 and .phi.2. For elements on the chip to function properly, it is important that edges of clock signals .phi.1 and .phi.2 are non-overlapping. If the edges overlap there will be more restrictions on data transfer and signal hand shaking.
Additionally, it is equally important that non-overlapping clock edges be evenly distributed to all comers of a chip regardless of the distance which those signals must travel. As chip size increases, clock signals .phi.1 and .phi.2 have to travel greater distances throughout the chip. This causes clock signals .phi.1 and .phi.2 to become degraded. As distances increase, rising edges 202,206 and failing edges 204,208 may become obscured (experience phase shifts and increases in transition times) and can overlap. This phenomenon, sometimes referred to as clock skew, is caused by a number of factors, including: loading, unwanted noise, coupling, capacitance, resistance, inductance and other debilitating effects.
To account for these factors, designers must separate the rising and falling edges 202, 204, 206, 208 of different clock signals (i.e., .phi.1 and .phi.2 ) with a large enough margin of time to allow for clock skew. For instance, failing edge 204 and rising edge 206 must be separated by a minimum temporal distance or amount of time (7) to avoid overlapping states; especially for level-triggering operations in metal-oxide-silicon (MOS) technology.
The larger T is, the less likely the chip will fail due to overlapping signals caused by skewing. The wide range of operating environments to which the chip(s) may be subject must be considered in selecting T. Therefore, to provide an adequate margin, manufacturers are forced to select T large enough to provide functionality in a worst-case environment. However, a large T is a significant cycle time constraint. Therefore chip design is not optimized for each environment.
To illustrate this, consider current chip design practices that must account for clock skew by designing a chip with a minimum safety distance between signals against worst-case conditions. Once T is selected the chip is manufactured and tested. If the chip designer selected a clock speed that has insufficient non-overlapping time, the chip will not function due to overlapping states for some circuits located on the chip. When a chip runs properly, chip designers assume they have chosen the correct frequency, clock states; rise and fall times, and non-overlapping time T. However, chip designers do not know whether a faster clock speed or a smaller Tare possible. To find out, chip manufacturers must build entirely new chips with different process parameters, which is inefficient and expensive.
Presently, no programming or tweaking can be performed after a chip is finalized. It is possible to have an on-chip clock generator running at different clock frequencies than external crystal oscillators, but the non-overlapping time of the clock edges generated by the clock generator is fixed by circuit hardware. Therefore, what is needed is a flexible system and method of programming an on-chip clock generator at the manufacturing stage to achieve adjustable as well as optimal non-overlapping times T between clock edges.
At the post-manufacturing stage, environmental conditions, such as heat and cold can also affect clock skewing. If a chip is manufactured under laboratory conditions, it may function properly. However, temperature changes may cause the chip to malfunction due to skewed clock signals. Therefore, what is needed is an on-chip clock generator that can be dynamically programmed to select non-overlapping times T to account for environmental fluctuations while the chip is in an operational environment, such as a processor chip operating in a computer.